1. Field of the Invention
The present invention relates in general to a lead frame and a semiconductor package with such a lead frame and, more particularly, to a structural improvement in such a lead frame for removing a chip paddle from the lead frame but forming inner leads as well as outer leads of the lead frame using different metals, thereby improving operational reliability of a semiconductor package, and to a semiconductor package produced using such a lead frame.
2. Description of the Prior Art
With reference to FIG. 1, there is shown a typical lead frame for a semiconductor package. In the drawing, the reference numeral 2 denotes a chip paddle which is placed in the center of the lead frame between a pair of side rails 1 and 1a and held by a pair of tie bars 3. The paddle 2 will hold a semiconductor chip 10 thereon in a semiconductor package as shown in FIG. 2. The lead frame also includes a plurality of inner leads 4 radially extending about the paddle 2, which inner leads 4 will be electrically connected to a plurality of pads of the semiconductor chip 10 by means of a plurality of metal wires 13 respectively, which metal wires 13 will be bonded to the pads of the chip 10 and to the inner leads 4 at their opposed ends. Extending outward from the inner leads 4 are a plurality of outer leads 5, which outer leads 5 are connected to each other by means of dambars 6 crossing the outer leads 5 and will be mounted on the surface of a PCB (printed circuit board, not shown) when surface-mounting the package on the PCB. The above lead frame acts as a chip holder for holding the semiconductor chip 10 thereon, as an electric passage for transmitting signals relative to the chip 10 and as a thermal passage for radiating the heat evolved from the semiconductor chip 10 to the outside of the package.
FIG. 2 is a sectional view of a semiconductor package produced using the above lead frame. As shown in this drawing, the semiconductor chip 10 is fixedly attached, using a die attaching epoxy such as a thermosetting bonder 15, to the top surface of the paddle 2 of the lead frame 11 made of copper. The pads of the chip 10 are electrically connected to the inner leads 4 of the lead frame 11 by means of the metal wires 13 respectively. A predetermined volume including the chip 10, the inner leads 4 and the metal wires 13 is hermetically packaged using an epoxy molding compound, thus to form a package body 14. In this case, the outer leads 5 of the lead frame 11 extend to the outside of the package body 14 at opposed sides of the body 14. The above semiconductor package is mounted to the surface of the PCB (not shown) by mounting the outer leads 5 to the surface of the PCB.
In order to produce the above semiconductor package, a sawing step is primarily carried out for dividing a semiconductor wafer (not shown) into a plurality of semiconductor chips 10. The sawing step is followed by a die attaching step in which one of the semiconductor chips 10 is fixedly attached to the paddle 2 of the copper lead frame 11 using the thermosetting bonder 15. The lead frame 11 having the semiconductor chip 10 is, thereafter, cured for a predetermined time prior to a wire bonding step. In the wire bonding step, the pads of the chip 10 on the paddle 2 are electrically connected to the inner leads 4 of the lead frame 11 by means of the plurality of metal wires 13 respectively. The wire bonding step is followed by a package molding step. In the package molding step, the predetermined volume including the semiconductor chip 10, the inner leads 4 and the metal wires 13 is hermetically packaged using the epoxy molding compound, thus to form the package body 14. After forming the package body 14, the lead frame 11 packaged by the package body 14 is subjected to curing for a predetermined time in order for curing the package body 14. Thereafter, a trimming step is carried out for cutting the tie bars 3 of the lead frame 11 and for cutting the dambars 6, which dambars 6 have maintained the inner and outer leads 4 and 5 of the lead frame 11 in their places relative to the side rails 1 and 1a, thus to electrically separate each inner lead 4 and an associated outer lead 5 from the other inner and outer leads 4 and 5. The trimming step is followed by a forming step for forming the outer leads 5 into a predetermined configuration. The process for producing the above package of FIG. 2 is ended at a plating step. The semiconductor package produced through the above process is, thereafter, subjected to a performance test prior to surface mounting of the package on the PCB. The package mounted on the surface of the PCB outputs and inputs electric signals from and to the semiconductor chip 10 through the lead frame 11.
As described above, the typical lead frame 11 of the semiconductor package has the chip paddle 2 for holding the semiconductor chip 10 thereon, so that the package has a problem that it may have chip crack as well as interfacial separation due to difference of thermal expansion coefficient between the paddle 2, the chip 10 and the epoxy molding compound of the package body 14. In addition, as the volume ratio of the semiconductor chip 10 to the total volume defined by the package body 14 has been enlarged due to the recent tendency that the size of semiconductor chips has been enlarged more and more, the volume ratio of the package body 14 has been reduced. In this regard, the trimming step may cause a crack in the package body 14 made of the molding compound as well as cause a chip crack.
Furthermore, the typical lead frame 11 of the package is made of a single material or copper, so that the package inevitably suffers from deterioration due to the single material of the lead frame 11. Another problem of the above package is resided in that a plurality of packages can not be vertically layered even when the packages need to be layered in order to enlarge the memory capacity. The outer leads 5 of the lead frame 11 of the package have the downward extending configuration as shown in FIG. 2, so that the package inevitably wastes the space when the package is mounted on the surface of the PCB.